
MAX1437BETK+
UnknownOCTAL, 12-BIT, 50MSPS, 1.8V ADC WITH SERIAL LVDS OUTPUTS
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MAX1437BETK+
UnknownOCTAL, 12-BIT, 50MSPS, 1.8V ADC WITH SERIAL LVDS OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | MAX1437BETK+ |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | LVDS - Serial |
| Features | Simultaneous Sampling |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 8 |
| Number of Bits | 12 |
| Number of Inputs [custom] | 8 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 C |
| Package / Case | 68-WFQFN Exposed Pad |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | Internal, External |
| Sampling Rate (Per Second) | 50 M |
| Supplier Device Package | 68-TQFN (10x10) |
| Voltage - Supply, Analog [Max] | 1.9 V |
| Voltage - Supply, Analog [Min] | 1.7 V |
| Voltage - Supply, Digital [Max] [custom] | 5.5 V |
| Voltage - Supply, Digital [Min] [custom] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 0.00 | |
| 1740 | $ 0.00 | |||
Description
General part information
MAX1437B Series
The MAX1437B octal, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction incorporating a fully differential signal path. This ADC is optimized for low-power and high-dynamic performance in medical imaging instrumentation and digital communications applications. The MAX1437B operates from a 1.8V single supply and consumes only 768mW (96mW per channel) while delivering a 70.2dB (typ) signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1437B features a low-power standby mode for idle periods.An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise.A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip phase-locked loop (PLL) generates the high-speed serial low-voltage differential signal (LVDS) clock.The MAX1437B has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two's complement format.The MAX1437B offers a maximum sample rate of 50Msps. This device is available in a small, 10mm x 10mm x 0.8mm, 68-pin TQFN package with exposed pad and is specified for the extended industrial (-40°C to +85°C) temperature range.ApplicationsInstrumentationMultichannel CommunicationsUltrasound and Medical Imaging
Documents
Technical documentation and resources