CDC341DW
Active1-TO-8 TTL CLOCK DRIVER WITH OUTPUT CONTROL PINS FOR LOW STATE
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CDC341DW
Active1-TO-8 TTL CLOCK DRIVER WITH OUTPUT CONTROL PINS FOR LOW STATE
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Technical Specifications
Parameters and characteristics for this part
| Specification | CDC341DW |
|---|---|
| Differential - Input:Output | False |
| Frequency - Max [Max] | 80 MHz |
| Input | TTL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output | TTL |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Ratio - Input:Output | 1:8 |
| Supplier Device Package | 20-SOIC |
| Type | Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 5.25 V |
| Voltage - Supply [Min] | 4.75 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 75 | $ 14.03 | |
| Texas Instruments | TUBE | 1 | $ 12.90 | |
| 100 | $ 11.27 | |||
| 250 | $ 8.69 | |||
| 1000 | $ 7.77 | |||
Description
General part information
CDC341 Series
The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of the A input.
The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND.
The CDC341 is characterized for operation from 0°C to 70°C.
Documents
Technical documentation and resources
