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ADSP-21160NCBZ-100
Integrated Circuits (ICs)

ADSP-21160NCBZ-100

Active
Analog Devices Inc./Maxim Integrated

HIGH PERFORMANCE 32-BIT SHARC DSP, 100 MHZ

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ADSP-21160NCBZ-100
Integrated Circuits (ICs)

ADSP-21160NCBZ-100

Active
Analog Devices Inc./Maxim Integrated

HIGH PERFORMANCE 32-BIT SHARC DSP, 100 MHZ

Technical Specifications

Parameters and characteristics for this part

SpecificationADSP-21160NCBZ-100
Clock Rate (Frequency)100 MHz
InterfaceHost Interface, Serial Port, Link Port
Mounting TypeSurface Mount
Non-Volatile Memory TypeExternal
On-Chip RAM512 kB
Operating Temperature (Max)100 °C
Operating Temperature (Min)-40 °C
Package / Case400-BBGA
Package Length27 mm
Package Name400-PBGA
Package Width27 mm
TypeFloating Point
Voltage - Core1.9 V
Voltage - I/O3.3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$Updated
DigikeyTray 1$ 583.61<1d
10$ 521.50

CAD

3D models and CAD resources for this part

Description

General part information

ADSP-21160N Series

The ADSP-21160N SHARC®DSP is the second iteration of the ADSP-21160. Built in a 0.18 micron CMOS process, it offers higher performance and lower power consumption than its predecessor, the ADSP-21160M. Easing portability, the ADSP-21160N is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (Single Instruction, Single Data) mode. To take advantage of the processor’s SIMD (Single Instruction, Multiple Data) capability, some code changes are needed. Like other SHARCs, the ADSP-21160N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160N includes a 100 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.The ADSP-21160N introduces Single-Instruction, Multiple-Data (SIMD) processing. Using two computational units (ADSP-2106x SHARC DSPs have one), the ADSP-21160N can double performance versus the ADSP-2106x on a range of DSP algorithms.The ADSP-21160N continues SHARC’s industry-leading standards of integration for DSPs, combining a high-performance 32-bit DSP core with integrated, on-chip system features. These features include a 4M-bit dual ported SRAM memory, host processor interface, I/O processor that supports 14 DMA channels, two serial ports, six link ports, external parallel bus, and glueless multiprocessing.

Documents

Technical documentation and resources

ADSP-21160NCBZ-100 | Datasheet

Datasheet

EE-332: Cycle Counting and Profiling (Rev.2)

Application Note

Package Drawing - 400-Ball PBGA (27mm x 27mm)

Package Drawing

EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev.1)

Application Note

ADSP-21160N_SHARC_Anomaly_List_for_Revisions 0.0,0.1 (Rev.L)

Integrated Circuit Anomaly

EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev.1)

Application Note

EE-68: Analog Devices JTAG Emulation Technical Reference (Rev.10)

Application Note

EE-305: Designing and Debugging Systems with SHARC Processors (Rev.1)

Application Note

EE-140: Using the ADSP-21160 Serial Ports in Multi-channel Mode

Application Note

Summit-ICE PCI Emulator Hardware Installation Guide (Rev.4)

Legacy Emulator Manual

EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev.14)

Application Note

EE-195: Moving from the ADSP-21160M SHARC® DSP to the ADSP-21160N SHARC DSP

Application Note

EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev.3)

Application Note

EE-148: Introduction to SHARC® Multiprocessor Systems using VisualDSP++™

Application Note

EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev.2)

Application Note

EE-110: A Quick Primer on ELF and DWARF File Formats

Application Note

EE-134: Writing C Compatible Assembly Code Interrupt Handlers for the SHARC® Family

Application Note

ADSP-21160 SHARC®DSP Hardware Reference (Rev.4.1)

Processor Manual

EE-77: SHARC Link Port Booting

Application Note

EE-132: Placing C Code and Data Modules in SHARC memory using VisualDSP++™

Application Note

Apex-ICE USB Emulator Hardware Installation Guide (Rev.6.0)

Legacy Emulator Manual

EE-104: Setting Up Streams with the VisualDSP Debugger

Application Note

SHARC Processor Family

Product Highlight

EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev.2)

Application Note

EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs

Application Note

EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev.1)

Application Note

ADSP-21160 EZ-KIT Lite®Evaluation System Manual (Rev.5.0)

User Guide

EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev.1)

Application Note

EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev.3)

Application Note

EE-177: SHARC® SPI Slave Booting (Rev.3)

Application Note

EE-253: Power Bypass Decoupling of SHARC® Processors (Rev.1)

Application Note

EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev.1)

Application Note

EE-106: Link Port Open Systems Interconnect Cable Standard

Application Note

EE-141: Benchmarking C Code on the ADSP-2106x and the ADSP-2116x Family of DSPs

Application Note

EE-340: Connecting SHARC®and Blackfin®Processors over SPI (Rev.1)

Application Note

ADSP-21160 SHARC®DSP Instruction Set Reference (Rev.2.1)

Processor Manual

EE-160: Examining ADSP-21160 Link Port Backward Compatibility to the ADSP-2106x Link Ports

Application Note

EE-323: Implementing Dynamically Loaded Software Modules (Rev.1)

Application Note

EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev.1)

Application Note

EE-128: DSP in C++: Calling Assembly Class Member Functions From C++

Application Note

EE-284: Implementing Overlays on ADSP-21160 SHARC® Processors (Rev.1)

Application Note