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48-VQFN-Exposed-Pad-RGZ
Integrated Circuits (ICs)

ADS6242IRGZT

Active
Texas Instruments

DUAL-CHANNEL, 14-BIT, 65-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)

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48-VQFN-Exposed-Pad-RGZ
Integrated Circuits (ICs)

ADS6242IRGZT

Active
Texas Instruments

DUAL-CHANNEL, 14-BIT, 65-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)

Technical Specifications

Parameters and characteristics for this part

SpecificationADS6242IRGZT
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceLVDS - Serial
FeaturesSimultaneous Sampling
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters2
Number of Bits14
Number of Inputs2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case48-VFQFN Exposed Pad
Ratio - S/H:ADC1:1
Reference TypeExternal, Internal
Sampling Rate (Per Second)65 M
Supplier Device Package48-VQFN (7x7)
Voltage - Supply, Analog [Max]3.6 V
Voltage - Supply, Analog [Min]3 V
Voltage - Supply, Digital [Max]3.6 V
Voltage - Supply, Digital [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 65.88
Digi-Reel® 1$ 65.88
Tape & Reel (TR) 250$ 53.90
Texas InstrumentsSMALL T&R 1$ 60.48
100$ 53.76
250$ 44.19
1000$ 39.53

Description

General part information

ADS6242 Series

ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.

The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.