The 74ALVCH16500 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEAB andOEBA), latch enable (LEAB and LEBA), and clock (CPABandCPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition ofCPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.