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Analog Devices-LTC2234CUK#PBF Analog to Digital Converters - ADCs 1-Channel Single ADC Pipelined 135Msps 10-bit Parallel 48-Pin QFN EP Tube
Integrated Circuits (ICs)

LTC2123IUK#TRPBF

Active
Analog Devices Inc./Maxim Integrated

2-CHANNEL DUAL ADC PIPELINED 250MSPS 14-BIT JESD204B 48-PIN QFN EP T/R

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Analog Devices-LTC2234CUK#PBF Analog to Digital Converters - ADCs 1-Channel Single ADC Pipelined 135Msps 10-bit Parallel 48-Pin QFN EP Tube
Integrated Circuits (ICs)

LTC2123IUK#TRPBF

Active
Analog Devices Inc./Maxim Integrated

2-CHANNEL DUAL ADC PIPELINED 250MSPS 14-BIT JESD204B 48-PIN QFN EP T/R

Technical Specifications

Parameters and characteristics for this part

SpecificationLTC2123IUK#TRPBF
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceJESD204B
FeaturesSimultaneous Sampling
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters2
Number of Bits14
Number of Inputs2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 C
Package / Case48-WFQFN Exposed Pad
Ratio - S/H:ADC1:1
Reference TypeInternal, External
Sampling Rate (Per Second)250 M
Supplier Device Package48-QFN (7x7)
Voltage - Supply, Analog [Max]1.9 V
Voltage - Supply, Analog [Min]1.7 V
Voltage - Supply, Digital [Max] [custom]1.9 V
Voltage - Supply, Digital [Min] [custom]1.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$Updated
DigikeyN/A 0$ 192.601m+

Description

General part information

LTC2123 Series

The LTC2123 is a 2-channel simultaneous sampling 250Msps 14-bit A/D converter with serial JESD204B outputs. It is designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 70dBFS SNR and 90dBFS spurious free dynamic range (SFDR). The 1.25GHz input bandwidth allows the ADC to under-sample high frequencies.The 5Gbps JESD204B serial interface simplifies the PCB design by minimizing the number of data lines required.The DEVCLK+and DEVCLK–inputs can be driven differentially with sine wave, PECL, or LVDS signals. An optional clock divide-by-two circuit or clock duty cycle stabilizer maintains high performance at full speed for a wide range of clock duty cycles.ApplicationsCommunicationsCellular Base StationsSoftware Defined RadiosMedical ImagingHigh Definition VideoTest and Measurement Instrumentation