Specification	SN74AC564N

Clock Frequency	95 MHz
Current - Output High, Low	24 mA
Current - Quiescent (Iq)	4 çA
Function	Standard
Input Capacitance	4.5 pF
Max Propagation Delay @ V, Max CL	10.5 ns
Mounting Type	Through Hole
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State, Inverted
Package / Case	20-DIP
Package / Case	7.62 mm
Package / Case	0.3 in
Supplier Device Package	20-PDIP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

SN74AC564 Series

Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs

Part	Current - Quiescent (Iq)	Number of Bits per Element	Current - Output High, Low	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Function	Clock Frequency	Input Capacitance	Trigger Type	Number of Elements	Output Type	Package / Case	Package / Case	Package / Case	Supplier Device Package	Max Propagation Delay @ V, Max CL	Operating Temperature [Max]	Operating Temperature [Min]	Type	Package / Case [y]	Package / Case [x]	Package / Case [y]
Texas Instruments SN74AC564N	4 çA	8	24 mA	Through Hole	2 V	6 V	Standard	95 MHz	4.5 pF	Positive Edge	1	Tri-State Inverted	20-DIP	7.62 mm	0.3 in	20-PDIP	10.5 ns	85 °C	-40 °C	D-Type
Texas Instruments SN74AC564PWR	4 çA	8	24 mA	Surface Mount	2 V	6 V	Standard	95 MHz	4.5 pF	Positive Edge	1	Tri-State Inverted	20-TSSOP			20-TSSOP	10.5 ns	85 °C	-40 °C	D-Type	4.4 mm	0.173 in
Texas Instruments SN74AC564DBLE	4 çA	8	24 mA	Surface Mount	2 V	6 V	Standard	95 MHz	4.5 pF	Positive Edge	1	Tri-State Inverted	20-SSOP			20-SSOP	10.5 ns	85 °C	-40 °C	D-Type
Texas Instruments SN74AC564PW	4 çA	8	24 mA	Surface Mount	2 V	6 V	Standard	95 MHz	4.5 pF	Positive Edge	1	Tri-State Inverted	20-TSSOP			20-TSSOP	10.5 ns	85 °C	-40 °C	D-Type	4.4 mm	0.173 in
Texas Instruments SN74AC564NSRG4	4 çA	8	24 mA	Surface Mount	2 V	6 V	Standard	95 MHz	4.5 pF	Positive Edge	1	Tri-State Inverted	20-SOIC	5.3 mm	0.209 "	20-SO	10.5 ns	85 °C	-40 °C	D-Type
Texas Instruments SN74AC564DWR	4 çA	8	24 mA	Surface Mount	2 V	6 V	Standard	95 MHz	4.5 pF	Positive Edge	1	Tri-State Inverted	20-SOIC			20-SOIC	10.5 ns	85 °C	-40 °C	D-Type	0.295 in		7.5 mm
Texas Instruments SN74AC564DWRE4	4 çA	8	24 mA	Surface Mount	2 V	6 V	Standard	95 MHz	4.5 pF	Positive Edge	1	Tri-State Inverted	20-SOIC			20-SOIC	10.5 ns	85 °C	-40 °C	D-Type	0.295 in		7.5 mm
Texas Instruments SN74AC564DBR	4 çA	8	24 mA	Surface Mount	2 V	6 V	Standard	95 MHz	4.5 pF	Positive Edge	1	Tri-State Inverted	20-SSOP			20-SSOP	10.5 ns	85 °C	-40 °C	D-Type

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.57
		20	$ 1.41
		40	$ 1.33
		100	$ 1.14
		260	$ 1.07
		500	$ 0.94
Texas Instruments	TUBE	1	$ 2.55
		100	$ 2.10
		250	$ 1.51
		1000	$ 1.14

Description

General part information

SN74AC564 Series

The ’AC564 devices are octal D-type edge-triggered flip-flops that feature inverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

Documents

Technical documentation and resources

TI IBIS File Creation, Validation, and Distribution Processes

Application note

LOGIC Pocket Data Book (Rev. B)

User guide

SN74AC564 Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs datasheet (Rev. F)

Data sheet

SN74AC564N

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SN74AC564N

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Technical Specifications

SN74AC564 Series

Pricing

Description

SN74AC564 Series

Documents

TI IBIS File Creation, Validation, and Distribution Processes

LOGIC Pocket Data Book (Rev. B)

SN74AC564 Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs datasheet (Rev. F)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Live Insertion

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Power-Up Behavior of Clocked Devices (Rev. B)

HiRel Unitrode Power Management Brochure

CMOS Power Consumption and CPD Calculation (Rev. B)

Designing With Logic (Rev. C)

Logic Guide (Rev. AB)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Input and Output Characteristics of Digital Integrated Circuits

Implications of Slow or Floating CMOS Inputs (Rev. E)

SN74AC564 Series