Specification	74LVT16373ADGG,118

Circuit	8:8
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Delay Time - Propagation	2.1 ns
Independent Circuits	2
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 C
Output Type	Tri-State
Package / Case	48-TFSOP
Package / Case [x]	0.24 in
Package / Case [y]	6.1 mm
Supplier Device Package	48-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

74LVT16373ADGG Series

3.3 V 16-bit transparent D-type latch; 3-state

Part	Package / Case	Package / Case [y]	Package / Case [x]	Output Type	Circuit	Independent Circuits	Voltage - Supply [Max]	Voltage - Supply [Min]	Logic Type	Mounting Type	Delay Time - Propagation	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Current - Output High, Low [custom]	Current - Output High, Low [custom]
Nexperia USA Inc. 74LVT16373ADGG,118	48-TFSOP	6.1 mm	0.24 in	Tri-State	8:8	2	3.6 V	2.7 V	D-Type Transparent Latch	Surface Mount	2.1 ns	85 °C	-40 C	48-TSSOP	64 mA	32 mA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	8343	$ 1.15

Description

General part information

74LVT16373ADGG Series

The 74LVT16373A is a 16-bit D-type transparent latch with 3-state outputs. The device can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The device features two latch enables (1LE and 2LE) and two output enables (1OEand 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOEcauses the outputs to assume a high-impedance OFF-state. Operation of the nOEinput does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs

Documents

Technical documentation and resources