Specification	CDCM1804RGER

Differential - Input:Output [custom]	True
Differential - Input:Output [custom]	True
Frequency - Max [Max]	800 MHz
Input	HSTL, SSTL-2, LVDS, VML, LVPECL, CML, LVTTL
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	LVPECL, LVCMOS
Package / Case	24-VFQFN Exposed Pad
Ratio - Input:Output	1:4
Supplier Device Package	24-VQFN (4x4)
Type	Fanout Buffer (Distribution), Divider, Multiplexer
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

CDCM1804 Series

Part	Number of Circuits	Ratio - Input:Output	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Package / Case	Supplier Device Package	Frequency - Max [Max]	Voltage - Supply [Max]	Voltage - Supply [Min]	Type	Output	Input
Texas Instruments CDCM1804RGER	1	1:4	85 °C	-40 °C	Surface Mount	24-VFQFN Exposed Pad	24-VQFN (4x4)	800 MHz	3.6 V	3 V	Divider Fanout Buffer (Distribution) Multiplexer	LVCMOS LVPECL	CML HSTL LVDS LVPECL LVTTL SSTL-2 VML
Texas Instruments CDCM1804RTHR	1	1:4	85 °C	-40 °C	Surface Mount	24-VFQFN Exposed Pad	24-VQFN (4x4)	800 MHz	3.6 V	3 V	Divider Fanout Buffer (Distribution) Multiplexer	LVCMOS LVPECL	CML HSTL LVDS LVPECL LVTTL SSTL-2 VML
Texas Instruments CDCM1804RTHT	1	1:4	85 °C	-40 °C	Surface Mount	24-VFQFN Exposed Pad	24-VQFN (4x4)	800 MHz	3.6 V	3 V	Divider Fanout Buffer (Distribution) Multiplexer	LVCMOS LVPECL	CML HSTL LVDS LVPECL LVTTL SSTL-2 VML

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	3000	$ 7.05
Texas Instruments	LARGE T&R	1	$ 9.05
		100	$ 7.91
		250	$ 6.09
		1000	$ 5.45

Description

General part information

CDCM1804 Series

The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] andY[2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50-transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS output Y3. This output is delayed by 1.6 ns over the three LVPECL output stages to minimize noise impact during signal transitions.

The CDCM1804 has three control terminals, S0, S1, and S2, to select different output mode settings. The S[2:0] terminals are 3-level inputs and therefore allow up to 33= 27 combinations. Additionally, an enable terminal (EN) is provided to disable or enable all outputs simultaneously. The EN terminal is a 3-level input as well and extends the number of settings to 2 × 27 = 54.

The CDCM1804 is characterized for operation from -40°C to 85°C.

Documents

Technical documentation and resources

1:3 LVPECL Clock Buffer & Addl LVCMOS Output & Programmable Divider datasheet (Rev. E)

Data sheet

CDCM1802/CDCM1804

Application note