Integrated Circuits (ICs)

SN74LVT573DWR

Obsolete

Texas Instruments

LATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN SOIC T/R

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Integrated Circuits (ICs)

SN74LVT573DWR

Obsolete

Texas Instruments

LATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN SOIC T/R

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DocumentsDatasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVT573DWR

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Delay Time - Propagation	2.9 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	20-SOIC
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

SN74LVT573 Series

3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputs

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Logic Type	Output Type	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Circuit [custom]	Circuit [custom]	Independent Circuits	Package / Case	Package / Case [y]	Package / Case [y]	Delay Time - Propagation
Texas Instruments SN74LVT573DW	64 mA	32 mA	D-Type Transparent Latch	Tri-State	Surface Mount	2.7 V	3.6 V	85 °C	-40 °C	20-SOIC	8	8	1	20-SOIC	0.295 in	7.5 mm	2.9 ns
Texas Instruments SN74LVT573DWR	64 mA	32 mA	D-Type Transparent Latch	Tri-State	Surface Mount	2.7 V	3.6 V	85 °C	-40 °C	20-SOIC	8	8	1	20-SOIC	0.295 in	7.5 mm	2.9 ns

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

SN74LVT573 Series

These octal latches are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The eight latches of the 'LVT573 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Documents

Technical documentation and resources