SN74ABT821ADWR
Active10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
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SN74ABT821ADWR
Active10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ABT821ADWR |
|---|---|
| Clock Frequency | 125 MHz |
| Current - Output High, Low [custom] | 64 mA |
| Current - Output High, Low [custom] | 32 mA |
| Function | Standard |
| Input Capacitance | 3.5 pF |
| Max Propagation Delay @ V, Max CL | 6.2 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 10 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 24-SOIC |
| Package / Case [custom] | 7.5 mm |
| Package / Case [custom] | 0.295 in |
| Supplier Device Package | 24-SOIC |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.95 | |
| 10 | $ 1.75 | |||
| 25 | $ 1.65 | |||
| 100 | $ 1.41 | |||
| 250 | $ 1.32 | |||
| 500 | $ 1.16 | |||
| 1000 | $ 0.96 | |||
| Digi-Reel® | 1 | $ 1.95 | ||
| 10 | $ 1.75 | |||
| 25 | $ 1.65 | |||
| 100 | $ 1.41 | |||
| 250 | $ 1.32 | |||
| 500 | $ 1.16 | |||
| 1000 | $ 0.96 | |||
| Tape & Reel (TR) | 2000 | $ 0.89 | ||
| 6000 | $ 0.86 | |||
| 10000 | $ 0.83 | |||
| Texas Instruments | LARGE T&R | 1 | $ 1.47 | |
| 100 | $ 1.21 | |||
| 250 | $ 0.87 | |||
| 1000 | $ 0.66 | |||
Description
General part information
SN74ABT821A Series
These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the devices provide true data at the Q outputs.
A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
Documents
Technical documentation and resources
