Specification	74HC174PW-Q100J

Clock Frequency	107 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Current - Quiescent (Iq)	8 ÁA
Grade	Automotive
Input Capacitance	3.5 pF
Max Propagation Delay @ V, Max CL	28 ns
Mounting Type	Surface Mount
Number of Bits per Element [custom]	6
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Non-Inverted
Package / Case	16-TSSOP
Package / Case [y]	4.4 mm
Package / Case [y]	0.173 in
Qualification	AEC-Q100
Supplier Device Package	16-TSSOP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

74HC174PW-Q100 Series

Hex D-type flip-flop with reset; positive-edge trigger

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Max]	Voltage - Supply [Min]	Max Propagation Delay @ V, Max CL	Operating Temperature [Max]	Operating Temperature [Min]	Number of Bits per Element [custom]	Qualification	Input Capacitance	Mounting Type	Current - Quiescent (Iq)	Output Type	Trigger Type	Package / Case [y]	Package / Case	Package / Case [y]	Clock Frequency	Grade	Number of Elements	Supplier Device Package	Type
Nexperia USA Inc. 74HC174PW-Q100J	5.2 mA	5.2 mA	6 V	2 V	28 ns	125 °C	-40 °C	6	AEC-Q100	3.5 pF	Surface Mount	8 ÁA	Non-Inverted	Positive Edge	4.4 mm	16-TSSOP	0.173 in	107 MHz	Automotive	1	16-TSSOP	D-Type

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	0	$ 0.29
		29300	$ 0.29

Description

General part information

74HC174PW-Q100 Series

The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW onMRcauses the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.