
SN74LVT16646DL
Active3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
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SN74LVT16646DL
Active3.3-V ABT 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LVT16646DL |
|---|---|
| Current - Output High, Low [custom] | 64 mA |
| Current - Output High, Low [custom] | 32 mA |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | 3-State |
| Package / Case | 0.295 in |
| Package / Case | 56-BSSOP |
| Package / Case | 7.5 mm |
| Supplier Device Package | 56-SSOP |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 80 | $ 11.87 | |
| Texas Instruments | TUBE | 1 | $ 11.97 | |
| 100 | $ 10.46 | |||
| 250 | $ 8.06 | |||
| 1000 | $ 7.21 | |||
Description
General part information
SN74LVT16646 Series
The 'LVT16646 are 16-bit bus transceivers designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ´LVT16646.
Output-enable (OE\) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. The direction control (DIR) determines which bus receives data when OE\ is low. In the isolation mode (OE\ high), A data may be stored in one register and/or B data may be stored in the other register.
Documents
Technical documentation and resources