TVP70025IPZP
ActiveTRIPLE 10-BIT 90-MSPS VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL
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TVP70025IPZP
ActiveTRIPLE 10-BIT 90-MSPS VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL
Technical Specifications
Parameters and characteristics for this part
| Specification | TVP70025IPZP |
|---|---|
| Applications | Consumer Video |
| Control Interface | I2C |
| Function | Digitizer |
| Mounting Type | Surface Mount |
| Package / Case | 100-TQFP Exposed Pad |
| Supplier Device Package | 100-HTQFP (14x14) |
| Voltage - Supply [Max] | 3.6 V, 1.9 V |
| Voltage - Supply [Min] | 1.7 V, 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 11.69 | |
| 10 | $ 10.74 | |||
| 25 | $ 10.30 | |||
| 90 | $ 9.07 | |||
| 270 | $ 8.63 | |||
| 450 | $ 8.07 | |||
| 990 | $ 7.40 | |||
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 10.14 | |
| 100 | $ 8.27 | |||
| 250 | $ 6.50 | |||
| 1000 | $ 5.51 | |||
Description
General part information
TVP70025I Series
The TVP70025I is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 90 MHz. Therefore, it can be used for PC graphics digitizing up to WXGA (1440 × 900) resolution at a 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080i.
The TVP70025I is powered from 3.3-V and 1.8-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP70025I includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP70025I can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.
The TVP70025I also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 9 MHz to 90 MHz.
Documents
Technical documentation and resources