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34-PCM
Integrated Circuits (ICs)

DS1744WP-120+

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Analog Devices Inc./Maxim Integrated

Y2K-COMPLIANT, NONVOLATILE TIMEKEEPING RAMS

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34-PCM
Integrated Circuits (ICs)

DS1744WP-120+

Active
Analog Devices Inc./Maxim Integrated

Y2K-COMPLIANT, NONVOLATILE TIMEKEEPING RAMS

Technical Specifications

Parameters and characteristics for this part

SpecificationDS1744WP-120+
Current - Timekeeping (Max) [Max]2 mA
Date FormatYY-MM-DD-dd
FeaturesY2K, Leap Year, NVSRAM
InterfaceParallel
Memory Size32 kB
Mounting TypeSurface Mount
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case34-PowerCap™ Module
Supplier Device Package34-PowerCap Module
Time FormatHH:MM:SS (24 hr)
TypeClock/Calendar
Voltage - Supply [Max]3.63 V
Voltage - Supply [Min]2.97 V
Voltage - Supply, Battery3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$Updated
DigikeyTray 1$ 54.57<4d
10$ 44.91
40$ 41.49
120$ 39.58

Description

General part information

DS1744 Series

The DS1744 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 32k x 8 NV SRAM. User access to all registers within the DS1744 is accomplished with a byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1744 also contains its own power-fail circuitry that deselects the device when the VCCsupply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCCas errant access and update cycles are avoided.