
TLV5617AIDR
Active10-BIT, 2.5 US DUAL DAC, SERIAL INPUT, PGRMABLE SETTLING TIME
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TLV5617AIDR
Active10-BIT, 2.5 US DUAL DAC, SERIAL INPUT, PGRMABLE SETTLING TIME
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | TLV5617AIDR |
|---|---|
| Architecture | String DAC |
| Data Interface | SPI |
| Differential Output | False |
| INL/DNL (LSB) | 0.7 LSB, 0.1 LSB |
| Mounting Type | Surface Mount |
| Number of Bits [custom] | 10 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Voltage - Buffered |
| Package / Case | 8-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Reference Type | External |
| Settling Time | 10 µs |
| Supplier Device Package | 8-SOIC |
| Voltage - Supply, Analog | 5 V |
| Voltage - Supply, Analog [Max] | 3.3 V |
| Voltage - Supply, Analog [Min] | 2.7 V |
| Voltage - Supply, Digital | 5 V |
| Voltage - Supply, Digital [Max] | 3.3 V |
| Voltage - Supply, Digital [Min] | 2.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 6.63 | |
| 10 | $ 5.99 | |||
| 25 | $ 5.71 | |||
| 100 | $ 4.96 | |||
| 250 | $ 4.74 | |||
| 500 | $ 4.32 | |||
| 1000 | $ 3.76 | |||
| Digi-Reel® | 1 | $ 6.63 | ||
| 10 | $ 5.99 | |||
| 25 | $ 5.71 | |||
| 100 | $ 4.96 | |||
| 250 | $ 4.74 | |||
| 500 | $ 4.32 | |||
| 1000 | $ 3.76 | |||
| Tape & Reel (TR) | 2500 | $ 3.45 | ||
| Texas Instruments | LARGE T&R | 1 | $ 5.84 | |
| 100 | $ 4.76 | |||
| 250 | $ 3.74 | |||
| 1000 | $ 3.17 | |||
Description
General part information
TLV5617A Series
The TLV5617A is a dual 10-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface is compatible with TMS320, SPI™, QSPI™, and Microwire™ serial ports. It is programmed with a 16-bit serial string containing 4 control bits and 10 data bits.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation.
Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.
Documents
Technical documentation and resources