V62/24609-01XE
ActiveENHANCED-PRODUCT DUAL D-TYPE FLIP-FLOPS WITH CLEAR, PRESET AND INTEGRATED LEVEL SHIFTER
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V62/24609-01XE
ActiveENHANCED-PRODUCT DUAL D-TYPE FLIP-FLOPS WITH CLEAR, PRESET AND INTEGRATED LEVEL SHIFTER
Technical Specifications
Parameters and characteristics for this part
| Specification | V62/24609-01XE |
|---|---|
| Clock Frequency | 59.4 MHz |
| Current - Output High, Low [custom] | 8 mA |
| Current - Output High, Low [custom] | 8 mA |
| Current - Quiescent (Iq) | 2 µA |
| Function | Reset, Set(Preset) |
| Input Capacitance | 4 pF |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Complementary |
| Package / Case | 14-TSSOP |
| Package / Case [custom] | 0.173 " |
| Package / Case [custom] | 4.4 mm |
| Supplier Device Package | 14-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1.6 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 3000 | $ 1.17 | |
| 6000 | $ 1.13 | |||
| Texas Instruments | LARGE T&R | 1 | $ 1.92 | |
| 100 | $ 1.59 | |||
| 250 | $ 1.14 | |||
| 1000 | $ 0.86 | |||
Description
General part information
SN74LV2T74-EP Series
The SN74LV2T74-EP contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
The SN74LV2T74-EP contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.