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Technical Specifications
Parameters and characteristics for this part
| Specification | CD4724BF3A |
|---|---|
| Circuit | 1:8 |
| Current - Output High, Low [custom] | 6.8 mA |
| Current - Output High, Low [custom] | 6.8 mA |
| Delay Time - Propagation | 50 ns |
| Independent Circuits | 1 |
| Logic Type | D-Type, Addressable |
| Mounting Type | Through Hole |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | 1.81 mOhm |
| Package / Case | 7.62 mm, 0.3 in |
| Package / Case | 16-CDIP |
| Supplier Device Package | 16-CDIP |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 20.34 | |
| 100 | $ 17.77 | |||
| 250 | $ 13.70 | |||
| 1000 | $ 12.26 | |||
Description
General part information
CD4724B-MIL Series
CD4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.
Documents
Technical documentation and resources