Specification	74HC74PW-Q100,118

Clock Frequency [custom]	82 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Function	Set(Preset) and Reset
Grade	Automotive
Input Capacitance	3.5 pF
Max Propagation Delay @ V, Max CL	37 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	14-TSSOP
Package / Case [x]	0.173 ", 4.4 mm
Qualification	AEC-Q100
Supplier Device Package	14-TSSOP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

74HC74PW-Q100 Series

Dual D-type flip-flop with set and reset; positive edge-trigger

Part	Supplier Device Package	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Bits per Element	Grade	Number of Elements	Max Propagation Delay @ V, Max CL	Input Capacitance	Mounting Type	Clock Frequency [custom]	Trigger Type	Qualification	Type	Function	Package / Case [x]	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Operating Temperature [Max]	Operating Temperature [Min]	Output Type
Nexperia USA Inc. 74HC74PW-Q100,118	14-TSSOP	5.2 mA	5.2 mA	1	Automotive	2	37 ns	3.5 pF	Surface Mount	82 MHz	Positive Edge	AEC-Q100	D-Type	Set(Preset) and Reset	0.173 " 4.4 mm	14-TSSOP	6 V	2 V	125 °C	-40 °C	Complementary

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	0	$ 0.38
		337520	$ 0.38

Description

General part information

74HC74PW-Q100 Series

The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQoutputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.