Integrated Circuits (ICs)

74HC174D,653

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Nexperia USA Inc.

FLIP FLOP, 74HC174, D, 28 NS, 107 MHZ, 5.2 MA, 16 PINS, SOIC

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Integrated Circuits (ICs)

74HC174D,653

Active

Nexperia USA Inc.

FLIP FLOP, 74HC174, D, 28 NS, 107 MHZ, 5.2 MA, 16 PINS, SOIC

Deep-Dive with AI

DocumentsDatasheet Wave soldering profile +9

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	74HC174D,653

Clock Frequency	107 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Current - Quiescent (Iq)	8 ÁA
Input Capacitance	3.5 pF
Max Propagation Delay @ V, Max CL	28 ns
Mounting Type	Surface Mount
Number of Bits per Element [custom]	6
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Non-Inverted
Package / Case	16-SOIC
Package / Case	0.154 in, 3.9 mm
Supplier Device Package	16-SO
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

74HC174D Series

Hex D-type flip-flop with reset; positive-edge trigger

Part	Number of Bits per Element [custom]	Number of Elements	Current - Quiescent (Iq)	Input Capacitance	Package / Case	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	Max Propagation Delay @ V, Max CL	Trigger Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package	Clock Frequency	Output Type	Type	Mounting Type
Nexperia USA Inc. 74HC174D,653	6	1	8 ÁA	3.5 pF	16-SOIC	0.154 in 3.9 mm	125 °C	-40 °C	6 V	2 V	28 ns	Positive Edge	5.2 mA	5.2 mA	16-SO	107 MHz	Non-Inverted	D-Type	Surface Mount

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	3864	$ 0.55

Description

General part information

74HC174D Series

The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW onMRcauses the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.