
SN74LV4T00PWREP
ActiveENHANCED-PRODUCT FOUR-CHANNEL TWO-INPUT NAND GATE WITH INTEGRATED LEVEL SHIFTER
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SN74LV4T00PWREP
ActiveENHANCED-PRODUCT FOUR-CHANNEL TWO-INPUT NAND GATE WITH INTEGRATED LEVEL SHIFTER
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LV4T00PWREP |
|---|---|
| Current - Output High, Low [custom] | 8 mA |
| Current - Output High, Low [custom] | 8 mA |
| Input Logic Level - High [Max] | 2 V |
| Input Logic Level - High [Min] | 1.1 V |
| Input Logic Level - Low [Max] | 0.85 V |
| Input Logic Level - Low [Min] | 0.5 V |
| Logic Type | NAND Gate |
| Max Propagation Delay @ V, Max CL | 13 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 4 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 14-TSSOP |
| Package / Case [custom] | 0.173 " |
| Package / Case [custom] | 4.4 mm |
| Supplier Device Package | 14-TSSOP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1.6 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 3.51 | |
| 10 | $ 2.30 | |||
| 25 | $ 1.98 | |||
| 100 | $ 1.63 | |||
| 250 | $ 1.45 | |||
| 500 | $ 1.35 | |||
| 1000 | $ 1.26 | |||
| Digi-Reel® | 1 | $ 3.51 | ||
| 10 | $ 2.30 | |||
| 25 | $ 1.98 | |||
| 100 | $ 1.63 | |||
| 250 | $ 1.45 | |||
| 500 | $ 1.35 | |||
| 1000 | $ 1.26 | |||
| Tape & Reel (TR) | 3000 | $ 1.15 | ||
| 6000 | $ 1.10 | |||
| 9000 | $ 1.07 | |||
| Texas Instruments | LARGE T&R | 1 | $ 1.92 | |
| 100 | $ 1.59 | |||
| 250 | $ 1.14 | |||
| 1000 | $ 0.86 | |||
Description
General part information
SN74LV4T00-EP Series
The SN74LV4T00-EP contains four independent 2-input NAND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
The SN74LV4T00-EP contains four independent 2-input NAND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
Documents
Technical documentation and resources