AD6652BBCZ
Active12-BIT, 65 MSPS IF TO BASE BAND DIVERSITY RECEIVER
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AD6652BBCZ
Active12-BIT, 65 MSPS IF TO BASE BAND DIVERSITY RECEIVER
Technical Specifications
Parameters and characteristics for this part
| Specification | AD6652BBCZ |
|---|---|
| Frequency | 200 MHz |
| Function | IF to Baseband Receiver |
| Mounting Type | Surface Mount |
| Package / Case | CSPBGA, 256-BGA |
| Package Length | 17 mm |
| Package Name | 256-CSPBGA |
| Package Width | 17 mm |
| RF Type | CDMA2000, AMPS, CDMA, Cellular, W-CDMA, UMTS |
| Sample Rate (Maximum) | 65 MSPS |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | Updated |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 113.72 | <1d |
| 16 | $ 97.71 | |||
| 32 | $ 94.27 | |||
| 104 | $ 88.88 | |||
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Description
General part information
AD6652 Series
The AD6652 is a mixed-signal IF to baseband receiver consisting of dual 12-bit MSPS ADCs and a wideband multimode digital downconverter (DDC). The AD6652 is designed to support communications applications where low cost, small size, and versatility are desired. The AD6652 is also suitable for other applications in imaging, medical ultrasound, instrumentation, and test equipment.APPLICATIONSCommunicationsDiversity radio systems Multimode digital receivers:GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,IS95, IS136, CDMA2000, IMT-2000I/Q demodulation systemsSmart antenna systemsGeneral-purpose software radiosBroadband data applicationsInstrumentation and test equipmentPRODUCT HIGHLIGHTSIntegrated dual 12-bit 65 MSPS ADC.Integrated wideband digital downconverter (DDC).Proprietary, differential SHA input maintains excellent SNR performance for input frequencies up to 200 MHz.Crossbar-switched digital downconverter input ports.Digital resampling permits noninteger relationships between the ADC clock and the digital output data rate.Energy-saving power-down modes.32-bit NCOs with selectable amplitude and phase dithering for better than −100 dBc spurious performance.CIC filters with user-programmable decimation and interpolation factors.160-tap RAM coefficient filter for each DDC channel.Dual 16-bit parallel output ports and dual 8-bit link ports.8-bit microport for register programming, register read-back, and coefficient memory programming.
Documents
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