SN74AUC1G74DCTR
ActiveSINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
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SN74AUC1G74DCTR
ActiveSINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AUC1G74DCTR |
|---|---|
| Clock Frequency | 275 MHz |
| Current - Output High, Low [custom] | 9 mA |
| Current - Output High, Low [custom] | 9 mA |
| Current - Quiescent (Iq) | 10 µA |
| Function | Reset, Set(Preset) |
| Input Capacitance | 2.5 pF |
| Max Propagation Delay @ V, Max CL [Max] | 1.8 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Complementary |
| Supplier Device Package | SM8 |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 2.7 V |
| Voltage - Supply [Min] | 0.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.82 | |
| 10 | $ 0.51 | |||
| 25 | $ 0.43 | |||
| 100 | $ 0.33 | |||
| 250 | $ 0.28 | |||
| 500 | $ 0.25 | |||
| 1000 | $ 0.23 | |||
| Digi-Reel® | 1 | $ 0.82 | ||
| 10 | $ 0.51 | |||
| 25 | $ 0.43 | |||
| 100 | $ 0.33 | |||
| 250 | $ 0.28 | |||
| 500 | $ 0.25 | |||
| 1000 | $ 0.23 | |||
| Tape & Reel (TR) | 3000 | $ 0.20 | ||
| 6000 | $ 0.19 | |||
| 9000 | $ 0.18 | |||
| 15000 | $ 0.17 | |||
| 21000 | $ 0.17 | |||
| 30000 | $ 0.16 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.29 | |
| 100 | $ 0.20 | |||
| 250 | $ 0.15 | |||
| 1000 | $ 0.10 | |||
Description
General part information
SN74AUC1G74 Series
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, theCLRinput overrides thePREinput when they are both low.
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Documents
Technical documentation and resources
