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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALVCH16903DGVR |
|---|---|
| Current - Output High, Low | 24 mA |
| Logic Type | Universal Bus Driver |
| Mounting Type | Surface Mount |
| Number of Circuits | 12-Bit |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 0.173 in |
| Package / Case | 56-TFSOP |
| Package / Case [y] | 4.4 mm |
| Supplier Device Package | 56-TVSOP |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2.3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74ALVCH16903 Series
This 12-bit universal bus driver is designed for 2.3-V to 3.6-V VCCoperation.
The SN74ALVCH16903 has dual outputs and can operate as a buffer or an edge-triggered register. In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies. The YERR\ output, which is produced one cycle after APAR, is open drain.
MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered register. On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN\) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN\ is high, only data set up at the 9A-12A inputs is stored in their internal registers. When MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs. 11A/YERREN\ serves a dual purpose; it acts as a normal data bit and also enables YERR\ data to be clocked into the YERR\ output register.
Documents
Technical documentation and resources
