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74ALVT16373DGG,118
Integrated Circuits (ICs)

74ALVT16373DGG,118

Active
Nexperia USA Inc.

LATCH, 74ALVT16373, D TYPE TRANSPARENT, TRI STATE, 2.5 NS, 64 MA, 48 PINS, TSSOP

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Documents74ALVT16373DGG,118 | Datasheetplastic thin shrink small outline package; 48 leads; body width 6.1 mm+5
74ALVT16373DGG,118
Integrated Circuits (ICs)

74ALVT16373DGG,118

Active
Nexperia USA Inc.

LATCH, 74ALVT16373, D TYPE TRANSPARENT, TRI STATE, 2.5 NS, 64 MA, 48 PINS, TSSOP

Deep-Dive with AI

Documents74ALVT16373DGG,118 | Datasheetplastic thin shrink small outline package; 48 leads; body width 6.1 mm+5

Technical Specifications

Parameters and characteristics for this part

Specification74ALVT16373DGG,118
Circuit8:8
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Current - Output High, Low [custom]24 mA
Current - Output High, Low [custom]8 mA
Delay Time - Propagation2 ns
Independent Circuits2
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 C
Output TypeTri-State
Package / Case48-TFSOP
Package / Case [x]0.24 in
Package / Case [y]6.1 mm
Supplier Device Package48-TSSOP
Voltage - Supply [Max]3.6 V, 2.7 V
Voltage - Supply [Min]2.3 V, 3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBulk 418$ 0.88
N/A 288$ 2.38

Description

General part information

74ALVT16373DGG Series

The 74ALVT16373 is a 16-bit D-type transparent latch with 3-state outputs. The device can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The device features two latch enables (1LE and 2LE) and two output enables (1OEand 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOEcauses the outputs to assume a high-impedance OFF-state. Operation of the nOEinput does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs