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64 LFCSP-VQ
Integrated Circuits (ICs)

AD5372BCPZ-RL7

Obsolete
Analog Devices Inc./Maxim Integrated

IC DAC 16BIT V-OUT 56LFCSP

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64 LFCSP-VQ
Integrated Circuits (ICs)

AD5372BCPZ-RL7

Obsolete
Analog Devices Inc./Maxim Integrated

IC DAC 16BIT V-OUT 56LFCSP

Technical Specifications

Parameters and characteristics for this part

SpecificationAD5372BCPZ-RL7
ArchitectureString DAC
Data InterfaceDSP, SPI
Differential OutputNo
DNL (Max) (LSB)1 LSB
INL (Max) (LSB)4 LSB
Mounting TypeSurface Mount
Number of Bits16 bits
Number of D/A Converters32 count
Operating Temperature (Max)85 °C
Operating Temperature (Min)-40 °C
Output TypeVoltage - Buffered
Package / CaseCSP, 64-VFQFN Exposed Pad
Package Length9 mm
Package Name64-LFCSP-VQ
Package Width9 mm
Reference TypeExternal
Settling Time30 µs
Voltage - Supply, Analog (Range 1 Max)16.5 V
Voltage - Supply, Analog (Range 1 Min)9 V
Voltage - Supply, Analog (Range 2 Max)16.5 V
Voltage - Supply, Analog (Range 2 Min)-4.5 V
Voltage - Supply, Digital (Max)5.5 V
Voltage - Supply, Digital (Min)2.5 V

Pricing

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CAD

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Description

General part information

AD5372 Series

The AD5372 /AD5373contain 32, 16-bit or 14-bit digital-to-analog converters (DACs) in a single 64-lead LQFP. The devices provide buffered voltage outputs with a nominal span of 4× the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into four groups of eight DACs. Two offset DACs allow the output range of the groups to be altered. Group 0 can be adjusted by Offset DAC 0, and Group 1 to Group 3 can be adjusted by Offset DAC 1.The AD5372 / AD5373 offer guaranteed operation over a wide supply range: VSSfrom −16.5 V to −4.5 V and VDDfrom 9 V to 16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.The AD5372 / AD5373 have a high-speed serial interface, which is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.The DAC registers are updated on reception of new data. All the outputs can be updated simultaneously by taking theLDACinput low. Each channel has a programmable gain and an offset adjust register.Each DAC output is gained and buffered on-chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via theCLRpin.APPLICATIONSLevel setting in automatic test equipment (ATE)Variable optical attenuators (VOA)Optical switchesIndustrial control systemsInstrumentation