
CY62128ELL-45ZXIT
ActiveSRAM, ASYNCHRONOUS SRAM, 1 MBIT, 128K X 8BIT, TSOP-I, 32 PINS, 4.5 V
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CY62128ELL-45ZXIT
ActiveSRAM, ASYNCHRONOUS SRAM, 1 MBIT, 128K X 8BIT, TSOP-I, 32 PINS, 4.5 V
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Technical Specifications
Parameters and characteristics for this part
| Specification | CY62128ELL-45ZXIT |
|---|---|
| Access Time | 45 ns |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization | 128 K |
| Memory Size | 1 Mbit |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -40 ¯C |
| Package / Case | 0.724 in |
| Package / Case | 32-TFSOP |
| Package / Case [custom] | 18.4 mm |
| Supplier Device Package | 32-TSOP I |
| Technology | SRAM - Asynchronous |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
| Write Cycle Time - Word, Page [custom] | 45 ns |
| Write Cycle Time - Word, Page [custom] | 45 ns |
| Part | Voltage - Supply [Max] | Voltage - Supply [Min] | Technology | Memory Size | Memory Format | Memory Type | Write Cycle Time - Word, Page | Supplier Device Package | Memory Organization | Operating Temperature [Max] | Operating Temperature [Min] | Mounting Type | Access Time | Memory Interface | Package / Case | Package / Case | Write Cycle Time - Word, Page [custom] | Write Cycle Time - Word, Page [custom] | Package / Case [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INFINEON | 3.6 V | 2.2 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 55 ns | 32-SOIC | 128 K | 85 C | -40 ¯C | Surface Mount | 55 ns | Parallel | 32-SOIC | 0.445 in 11.3 mm | |||
INFINEON | 5.5 V | 4.5 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 32-TSOP I | 128 K | 85 C | -40 ¯C | Surface Mount | 45 ns | Parallel | 32-TFSOP | 0.724 in | 45 ns | 45 ns | 18.4 mm | |
INFINEON | 5.5 V | 4.5 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 70 ns | 32-SOIC | 128 K | 70 °C | 0 °C | Surface Mount | 70 ns | Parallel | 32-SOIC | 0.445 in 11.3 mm | |||
INFINEON | 5.5 V | 4.5 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 70 ns | 32-TSOP I | 128 K | 85 C | -40 ¯C | Surface Mount | 70 ns | Parallel | 32-TFSOP | 0.724 in | 18.4 mm | ||
INFINEON | 5.5 V | 4.5 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 32-sTSOP | 128 K | 85 C | -40 ¯C | Surface Mount | 45 ns | Parallel | 32-TFSOP (0.465" 11.80mm Width) | 45 ns | 45 ns | |||
INFINEON | 3.6 V | 2.2 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 70 ns | 32-SOIC | 128 K | 85 C | -40 ¯C | Surface Mount | 70 ns | Parallel | 32-SOIC | 0.445 in 11.3 mm | |||
INFINEON | 3.6 V | 2.7 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 55 ns | 32-TSOP | 128 K | 85 C | -40 ¯C | Surface Mount | 55 ns | Parallel | 32-TFSOP (0.465" 11.80mm Width) | ||||
INFINEON | 5.5 V | 4.5 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 55 ns | 32-sTSOP | 128 K | 125 °C | -40 °C | Surface Mount | 55 ns | Parallel | 32-TFSOP (0.465" 11.80mm Width) | ||||
INFINEON | 5.5 V | 4.5 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 70 ns | 32-TSOP I | 128 K | 85 C | -40 ¯C | Surface Mount | 70 ns | Parallel | 32-TFSOP | 0.724 in | 18.4 mm | ||
INFINEON | 3.6 V | 2.7 V | SRAM - Asynchronous | 1 Mbit | SRAM | Volatile | 70 ns | 32-TSOP | 128 K | 70 °C | 0 °C | Surface Mount | 70 ns | Parallel | 32-TFSOP (0.465" 11.80mm Width) |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
CY62128 Series
CY62128ELL-45ZXIT is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features an advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (active-low CE1 HIGH or CE2 LOW). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (active-low CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (active-low CE1 LOW and CE2 HIGH and active-low WE LOW). The CY62128E device is suitable for interfacing with processors that have TTL I/P levels.
Documents
Technical documentation and resources