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SOT108-1
Integrated Circuits (ICs)

74HCT107D-Q100J

Active
Nexperia USA Inc.

FLIP FLOPS DUAL JK FLIP-FLOP WITH SET AND RESET; POSITIVE-EDGE-TRIGGER

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SOT108-1
Integrated Circuits (ICs)

74HCT107D-Q100J

Active
Nexperia USA Inc.

FLIP FLOPS DUAL JK FLIP-FLOP WITH SET AND RESET; POSITIVE-EDGE-TRIGGER

Technical Specifications

Parameters and characteristics for this part

Specification74HCT107D-Q100J
Clock Frequency66 MHz
Current - Output High, Low [custom]4 mA
Current - Output High, Low [custom]4 mA
Current - Quiescent (Iq)4 çA
FunctionReset
GradeAutomotive
Input Capacitance3.5 pF
Max Propagation Delay @ V, Max CL17 ns
Mounting TypeSurface Mount
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Package / Case3.9 mm, 0.154 in
Package / Case14-SOIC
QualificationAEC-Q100
Supplier Device Package14-SO
Trigger TypeNegative Edge
TypeJK Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyN/A 0$ 0.40
41866$ 0.40
MouserN/A 1$ 0.40
100$ 0.37
250$ 0.35
1000$ 0.31
2500$ 0.17

Description

General part information

74HCT107D-Q100 Series

The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q andQoutputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.