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54-WFQFN Exposed Pad
Integrated Circuits (ICs)

DS100KR800SQE/NOPB

Active
Texas Instruments

10.3-GBPS 8 CHANNEL (UNI-DIRECTIONAL) REDRIVER WITH EQ AND DE

54-WFQFN Exposed Pad
Integrated Circuits (ICs)

DS100KR800SQE/NOPB

Active
Texas Instruments

10.3-GBPS 8 CHANNEL (UNI-DIRECTIONAL) REDRIVER WITH EQ AND DE

Technical Specifications

Parameters and characteristics for this part

SpecificationDS100KR800SQE/NOPB
Data Rate (Max)10.3 Gbps
Delay Time200 ps
InputCML
Mounting TypeSurface Mount
Number of Channels8
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
OutputCML
Package / Case54-WFQFN Exposed Pad
Signal ConditioningInput Equalization, Output De-Emphasis
Supplier Device Package54-WQFN (10x5.5)
TypeReDriver, Buffer
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]2.375 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 20.48
Digi-Reel® 1$ 20.48
Tape & Reel (TR) 250$ 15.39
500$ 14.64
Texas InstrumentsSMALL T&R 1$ 17.44
100$ 15.23
250$ 11.75
1000$ 10.51

Description

General part information

DS100KR800 Series

The DS100KR800 device is a high performance repeater designed to support 8-channel (unidirectional), 10G-KR, and other high-speed interface serial protocols up to 10.3 Gbps. The continuous time linear equalizer (CTLE) of the receiver provides a boost of up to 36 dB at 5 GHz (10.3125 Gbps) in each of its eight channels. This equalizer is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as long backplanes or cables. The transmitter provides a de-emphasis boost of up to –12 dB and output voltage amplitude control from 700 mV to 1300 mV.

When operating in 10G-KR mode, the DS100KR800 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients as defined in the 802.3ap standard. This seamless management of the link training protocol ensures system level interoperability with minimum latency.

The programmable settings can be applied through pin settings, SMBus (I2C) protocol or an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power-up. This eliminates the need for an external microprocessor or software driver.