SN74ALS374ADWR
ActiveOCTAL D-TYPE EDGE TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
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SN74ALS374ADWR
ActiveOCTAL D-TYPE EDGE TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALS374ADWR |
|---|---|
| Clock Frequency | 35 MHz |
| Current - Output High, Low [custom] | 24 mA |
| Current - Output High, Low [custom] | 2.6 mA |
| Current - Quiescent (Iq) | 19 mA |
| Function | Standard |
| Max Propagation Delay @ V, Max CL | 16 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 20-SOIC |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.11 | |
| 10 | $ 0.99 | |||
| 25 | $ 0.94 | |||
| 100 | $ 0.77 | |||
| 250 | $ 0.72 | |||
| 500 | $ 0.64 | |||
| 1000 | $ 0.50 | |||
| Digi-Reel® | 1 | $ 1.11 | ||
| 10 | $ 0.99 | |||
| 25 | $ 0.94 | |||
| 100 | $ 0.77 | |||
| 250 | $ 0.72 | |||
| 500 | $ 0.64 | |||
| 1000 | $ 0.50 | |||
| Tape & Reel (TR) | 2000 | $ 0.47 | ||
| 6000 | $ 0.45 | |||
| 10000 | $ 0.43 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.90 | |
| 100 | $ 0.69 | |||
| 250 | $ 0.51 | |||
| 1000 | $ 0.36 | |||
Description
General part information
SN74ALS374A Series
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
Documents
Technical documentation and resources
