74AHC273D-Q100J
ActiveOCTAL D-TYPE FLIP-FLOP WITH RESET; POSITIVE-EDGE TRIGGER
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74AHC273D-Q100J
ActiveOCTAL D-TYPE FLIP-FLOP WITH RESET; POSITIVE-EDGE TRIGGER
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Technical Specifications
Parameters and characteristics for this part
| Specification | 74AHC273D-Q100J |
|---|---|
| Clock Frequency | 110 MHz |
| Current - Output High, Low [custom] | 8 mA |
| Current - Output High, Low [custom] | 8 mA |
| Current - Quiescent (Iq) | 4 çA |
| Grade | Automotive |
| Input Capacitance | 3 pF |
| Max Propagation Delay @ V, Max CL | 10.5 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element [custom] | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Non-Inverted |
| Package / Case | 20-SOIC (0.295", 7.50mm Width) |
| Qualification | AEC-Q100 |
| Supplier Device Package | 20-SO |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 1910 | $ 0.82 | |
Description
General part information
74AHC273D-Q100 Series
The 74AHC273-Q100; 74AHCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW onMRforces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
Documents
Technical documentation and resources