Zenode.ai Logo
Beta
54-BGA-Micro-Jr-GRD
Integrated Circuits (ICs)

74LCX16373GX

Obsolete
ON Semiconductor

IC LATCH TRANSP 16BIT LV 54FBGA

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsDatasheet
54-BGA-Micro-Jr-GRD
Integrated Circuits (ICs)

74LCX16373GX

Obsolete
ON Semiconductor

IC LATCH TRANSP 16BIT LV 54FBGA

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

Specification74LCX16373GX
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low24 mA
Delay Time - Propagation5.4 ns
Independent Circuits2
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case54-LFBGA
Supplier Device Package54-FBGA (5.5x8)
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$

Description

General part information

MC74LCX16373 Series

The MC74LCX16373 is a high performance, non-inverting 16-bit transparent latch operating from a 2.3 to 3.6V supply. The device is byte controlled. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16-bit operation. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VIspecification of 5.5V allows MC74LCX16373 inputs to be safely driven from 5V devices.The MC74LCX16373 contains 16 D-type latches with 3-state 5V-tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state outputs are controlled by the Output Enable(OEnbar) inputs. When OEbar is LOW, the outputs are enabled. When OEbar is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.

Documents

Technical documentation and resources