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Technical Specifications
Parameters and characteristics for this part
| Specification | CD4073BPWR |
|---|---|
| Current - Output High, Low [custom] | 3.4 mA |
| Current - Output High, Low [custom] | 3.4 mA |
| Current - Quiescent (Max) [Max] | 1 çA |
| Input Logic Level - High [Max] | 11 V |
| Input Logic Level - High [Min] | 3.5 V |
| Input Logic Level - Low [Max] | 4 V |
| Input Logic Level - Low [Min] | 1.5 V |
| Logic Type | AND Gate |
| Max Propagation Delay @ V, Max CL | 90 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 3 |
| Number of Inputs | 3 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 14-TSSOP |
| Package / Case [custom] | 0.173 " |
| Package / Case [custom] | 4.4 mm |
| Supplier Device Package | 14-TSSOP |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.03 | |
| 10 | $ 0.64 | |||
| 25 | $ 0.54 | |||
| 100 | $ 0.42 | |||
| 250 | $ 0.36 | |||
| 500 | $ 0.33 | |||
| 1000 | $ 0.30 | |||
| Digi-Reel® | 1 | $ 1.03 | ||
| 10 | $ 0.64 | |||
| 25 | $ 0.54 | |||
| 100 | $ 0.42 | |||
| 250 | $ 0.36 | |||
| 500 | $ 0.33 | |||
| 1000 | $ 0.30 | |||
| Tape & Reel (TR) | 2000 | $ 0.27 | ||
| 4000 | $ 0.25 | |||
| 6000 | $ 0.24 | |||
| 10000 | $ 0.23 | |||
| 14000 | $ 0.22 | |||
| 20000 | $ 0.22 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.41 | |
| 100 | $ 0.28 | |||
| 250 | $ 0.21 | |||
| 1000 | $ 0.14 | |||
Description
General part information
CD4073B Series
CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.
The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.
Documents
Technical documentation and resources
