Specification	74LVC16374ADGG-Q1J

Clock Frequency	300 MHz
Current - Output High, Low [custom]	24 mA
Current - Output High, Low [custom]	24 mA
Current - Quiescent (Iq)	20 çA
Function	Standard
Grade	Automotive
Input Capacitance	5 pF
Max Propagation Delay @ V, Max CL	5.4 ns
Mounting Type	Surface Mount
Number of Bits per Element [custom]	8
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Non-Inverted, Tri-State
Package / Case	48-TFSOP
Package / Case [x]	0.24 in
Package / Case [y]	6.1 mm
Qualification	AEC-Q100
Supplier Device Package	48-TSSOP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

74LVC16374ADGG-Q100 Series

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Input Capacitance	Operating Temperature [Max]	Operating Temperature [Min]	Trigger Type	Package / Case	Package / Case [y]	Package / Case [x]	Number of Bits per Element [custom]	Qualification	Max Propagation Delay @ V, Max CL	Function	Type	Grade	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Elements	Current - Quiescent (Iq)	Mounting Type	Output Type	Clock Frequency	Supplier Device Package
Nexperia USA Inc. 74LVC16374ADGG-Q1J	24 mA	24 mA	5 pF	125 °C	-40 °C	Positive Edge	48-TFSOP	6.1 mm	0.24 in	8	AEC-Q100	5.4 ns	Standard	D-Type	Automotive	1.65 V	3.6 V	2	20 çA	Surface Mount	Non-Inverted Tri-State	300 MHz	48-TSSOP

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	0	$ 1.21

Description

General part information

74LVC16374ADGG-Q100 Series

The 74LVC16374A-Q100; 74LVCH16374A-Q100 is a 16-bit edge-triggered D-type flip-flop with 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OEand 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOEcauses the outputs to assume a high-impedance OFF-state. Operation of the nOEinput does not affect the state of the flip-flops . Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Documents

Technical documentation and resources