Integrated Circuits (ICs)

CY7C1021DV33-10ZSXIT

LTB

INFINEON

SRAM, ASYNCHRONOUS SRAM, 1 MBIT, 64K X 16BIT, TSOP-II, 44 PINS, 3 V

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DocumentsCY7C1021DV33-10ZSXIT | Datasheet

Integrated Circuits (ICs)

CY7C1021DV33-10ZSXIT

LTB

INFINEON

SRAM, ASYNCHRONOUS SRAM, 1 MBIT, 64K X 16BIT, TSOP-II, 44 PINS, 3 V

Deep-Dive with AI

DocumentsCY7C1021DV33-10ZSXIT | Datasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CY7C1021DV33-10ZSXIT

Access Time	10 ns
Memory Format	SRAM
Memory Interface	Parallel
Memory Organization [custom]	64 K
Memory Organization [custom]	16
Memory Size	1 Mbit
Memory Type	Volatile
Mounting Type	Surface Mount
Operating Temperature [Max]	85 C
Operating Temperature [Min]	-40 ¯C
Package / Case	44-TSOP (0.400", 10.16mm Width)
Supplier Device Package	44-TSOP II
Technology	SRAM - Asynchronous
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V
Write Cycle Time - Word, Page	10 ns

CY7C1021DV33 Series

Part	Access Time	Memory Type	Memory Size	Package / Case	Memory Interface	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Memory Organization [custom]	Memory Organization [custom]	Write Cycle Time - Word, Page	Memory Format	Technology	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]
INFINEON CY7C1021DV33-10ZSXIT	10 ns	Volatile	1 Mbit	44-TSOP (0.400" 10.16mm Width)	Parallel	85 C	-40 ¯C	44-TSOP II	64 K	16	10 ns	SRAM	SRAM - Asynchronous	Surface Mount	3.6 V	3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	1265	$ 2.66
Mouser	N/A	1	$ 2.66
		10	$ 2.49
		25	$ 2.36
		100	$ 2.30
		250	$ 2.23
		500	$ 2.18
		1000	$ 1.90
		2000	$ 1.82
		5000	$ 1.80
Newark	Each	1	$ 3.16
		10	$ 2.60
		25	$ 2.53
		50	$ 2.46
		100	$ 2.39
		250	$ 2.35
		500	$ 2.31

Description

General part information

CY7C1021DV33 Series

CY7C1021DV33-10ZSXIT is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking chip enable (active-low CE) and write enable (active-low WE) inputs LOW. Reading from the device is accomplished by taking chip enable (active-low CE) and output enable (active-low OE) LOW while forcing the write enable (active-low WE) HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (active-low CE HIGH), the outputs are disabled (active-low OE HIGH), the active-low BHE and active-low BLE are disabled (active-low BHE, active-low BLE HIGH), or during a write operation (active-low CE LOW, and active-low WE LOW).

Documents

Technical documentation and resources

CY7C1021DV33-10ZSXIT | Datasheet

Datasheet