The 8305I-02 is a low skew, 1-to-4, differential/LVCMOS-to-LVCMOS/LVTTL fanout buffer. The 8305I-02 has selectable clock inputs that accept either differential or single-ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin. Outputs are forced low when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the 8305I-02 ideal for those applications demanding well-defined performance and repeatability.