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INFINEON CY7C1041GE30-10ZSXI
Integrated Circuits (ICs)

CY62157ESL-45ZSXI

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INFINEON

SRAM CHIP ASYNC SINGLE 2.5V/3.3V/5V 8M-BIT 512K X 16 45NS 44-PIN TSOP-II TRAY

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INFINEON CY7C1041GE30-10ZSXI
Integrated Circuits (ICs)

CY62157ESL-45ZSXI

Active
INFINEON

SRAM CHIP ASYNC SINGLE 2.5V/3.3V/5V 8M-BIT 512K X 16 45NS 44-PIN TSOP-II TRAY

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCY62157ESL-45ZSXI
Access Time45 ns
Memory FormatSRAM
Memory InterfaceParallel
Memory Organization512K x 16
Memory Size1024 KB
Memory TypeVolatile
Mounting TypeSurface Mount
Operating Temperature [Max]85 C
Operating Temperature [Min]-40 ¯C
Package / Case44-TSOP (0.400", 10.16mm Width)
Supplier Device Package44-TSOP II
TechnologySRAM - Asynchronous
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2.2 V
Write Cycle Time - Word, Page [custom]45 ns
Write Cycle Time - Word, Page [custom]45 ns

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 1$ 11.50
5$ 9.84
10$ 9.61
50$ 9.59
100$ 9.57
DigikeyN/A 270$ 8.50
Tray 1$ 14.52
10$ 12.89
25$ 12.30
40$ 12.00
80$ 11.58
230$ 10.96
440$ 10.59
945$ 10.18
NewarkEach 1$ 11.34
10$ 10.83
25$ 10.48
50$ 9.94
100$ 9.58
250$ 9.19
500$ 9.03

Description

General part information

CY62157 Series

CY62157ESL-45ZSXI is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected (active-low CE HIGH or both active-low BHE and active-low BLE are HIGH). The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (active-low CE HIGH), the outputs are disabled (active-low OE HIGH), both the byte high enable and the byte low enable are disabled (active-low BHE, active-low BLE HIGH), or during an active write operation (active-low CE LOW and active-low WE LOW). This device is suitable for interfacing with processors that have TTL I/P levels.

Documents

Technical documentation and resources