TSB12LV26TPZEP
NRNDENHANCED PRODUCT OHCI-LYNX PCI-BASED IEEE 1394 HOST CONTROLLER
Deep-Dive with AI
Search across all available documentation for this part.
TSB12LV26TPZEP
NRNDENHANCED PRODUCT OHCI-LYNX PCI-BASED IEEE 1394 HOST CONTROLLER
Technical Specifications
Parameters and characteristics for this part
| Specification | TSB12LV26TPZEP |
|---|---|
| Function | Controller |
| Interface | PCI |
| Operating Temperature [Max] | 105 ░C |
| Operating Temperature [Min] | -40 C |
| Package / Case | 100-LQFP |
| Protocol | IEEE 1394 |
| Standards | IEEE 1394a-2000, OHCI-Lynx™ |
| Supplier Device Package | 100-LQFP (14x14) |
| Voltage - Supply | 3.3 V, 5 VDC |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 21.71 | |
| Tray | 90 | $ 17.36 | ||
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 21.59 | |
| 100 | $ 18.86 | |||
| 250 | $ 14.54 | |||
| 1000 | $ 13.01 | |||
Description
General part information
TSB12LV26-EP Series
The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with thePCI Local Bus Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and1394 Open Host Controller Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, and 400M bits/s serial bus data rates.
As required by the1394 Open Host Controller Interface Specification(OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26 device is compliant with thePCI Bus Power Management Interface Specification, per thePC 99 Design Guiderequirements. TSB12LV26 device supports the D0, D2, and D3 power states.
The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data.
Documents
Technical documentation and resources