Specification	74LVC86APW,118

Current - Output High, Low [custom]	24 mA
Current - Output High, Low [custom]	24 mA
Current - Quiescent (Max) [Max]	40 µA
Input Logic Level - High [Max]	2 V
Input Logic Level - High [Min]	1.07 V
Input Logic Level - Low [Max]	0.8 V
Input Logic Level - Low [Min]	0.58 V
Logic Type	XOR (Exclusive OR)
Max Propagation Delay @ V, Max CL	5 ns
Mounting Type	Surface Mount
Number of Circuits	4
Number of Inputs	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 C
Package / Case	14-TSSOP
Package / Case [x]	0.173 ", 4.4 mm
Supplier Device Package	14-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.2 V

74LVC86APW Series

Quad 2-input EXCLUSIVE-OR gate

Part	Max Propagation Delay @ V, Max CL	Input Logic Level - High [Min]	Input Logic Level - High [Max]	Current - Quiescent (Max) [Max]	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package	Input Logic Level - Low [Min]	Input Logic Level - Low [Max]	Package / Case [x]	Package / Case	Logic Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Circuits	Number of Inputs	Operating Temperature [Max]	Operating Temperature [Min]
Nexperia USA Inc. 74LVC86APW,118	5 ns	1.07 V	2 V	40 µA	Surface Mount	24 mA	24 mA	14-TSSOP	0.58 V	0.8 V	0.173 " 4.4 mm	14-TSSOP	XOR (Exclusive OR)	3.6 V	1.2 V	4	2	125 °C	-40 C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	2040	$ 0.28

Description

General part information

74LVC86APW Series

The 74LVC86A is a quad 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Documents

Technical documentation and resources

Quad 2-input EXCLUSIVE-OR gate

Data sheet

TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation

Packing information

plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body

Package information

plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body

Marcom graphics

74LVC86APW,118

Deep-Dive with AI

74LVC86APW,118

Deep-Dive with AI

Technical Specifications

74LVC86APW Series

Pricing

Description

74LVC86APW Series

Documents

Quad 2-input EXCLUSIVE-OR gate

TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation

plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body

plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body

Power considerations when using CMOS and BiCMOS logic devices

Nexperia package poster

Footprint for wave soldering

74LVC86APW Nexperia Product Reliability

Pin FMEA for LVC family

74LVC86APW Series