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Nexperia-74LVC2G08DC,125 Logic Gates AND Gate 2-Element 2-IN CMOS 8-Pin VSSOP T/R
Integrated Circuits (ICs)

74AUP2G79DC,125

Active
Nexperia USA Inc.

FLIP FLOP D-TYPE POS-EDGE PUSH-PULL 2-ELEMENT AUTOMOTIVE 8-PIN VSSOP T/R

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Nexperia-74LVC2G08DC,125 Logic Gates AND Gate 2-Element 2-IN CMOS 8-Pin VSSOP T/R
Integrated Circuits (ICs)

74AUP2G79DC,125

Active
Nexperia USA Inc.

FLIP FLOP D-TYPE POS-EDGE PUSH-PULL 2-ELEMENT AUTOMOTIVE 8-PIN VSSOP T/R

Technical Specifications

Parameters and characteristics for this part

Specification74AUP2G79DC,125
Clock Frequency309 MHz
Current - Output High, Low [custom]4 mA
Current - Output High, Low [custom]4 mA
Current - Quiescent (Iq)500 nA
FunctionStandard
Input Capacitance0.6 pF
Max Propagation Delay @ V, Max CL5.8 ns
Mounting TypeSurface Mount
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeNon-Inverted
Package / Case8-VFSOP
Package / Case [custom]2.3 mm
Package / Case [custom]0.091 "
Supplier Device Package8-VSSOP
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]0.8 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 5$ 0.37
DigikeyBulk 1998$ 0.15
N/A 2445$ 0.49

Description

General part information

74AUP2G79DC Series

The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.