Specification	FDC6302P

Configuration	2 P-Channel
Current - Continuous Drain (Id) @ 25°C	120 mA
Drain to Source Voltage (Vdss)	25 V
FET Feature	Logic Level Gate
Gate Charge (Qg) (Max) @ Vgs [Max]	0.31 nC
Input Capacitance (Ciss) (Max) @ Vds	11 pF
Mounting Type	Surface Mount
Operating Temperature [Max]	150 °C
Operating Temperature [Min]	-55 °C
Package / Case	TSOT-23-6, SOT-23-6 Thin
Power - Max [Max]	700 mW
Rds On (Max) @ Id, Vgs	10 Ohm
Supplier Device Package	SuperSOT™-6
Technology	MOSFET (Metal Oxide)
Vgs(th) (Max) @ Id	1.5 V

FDC6302P Series

Dual P-Channel Digital FET -25V, -0.12A, 10Ω

Part	Input Capacitance (Ciss) (Max) @ Vds	Technology	Gate Charge (Qg) (Max) @ Vgs [Max]	Current - Continuous Drain (Id) @ 25°C	Vgs(th) (Max) @ Id	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Power - Max [Max]	Rds On (Max) @ Id, Vgs	Supplier Device Package	Package / Case	Drain to Source Voltage (Vdss)	Configuration	FET Feature
ON Semiconductor FDC6302P	11 pF	MOSFET (Metal Oxide)	0.31 nC	120 mA	1.5 V	-55 °C	150 °C	Surface Mount	700 mW	10 Ohm	SuperSOT™-6	SOT-23-6 Thin TSOT-23-6	25 V	2 P-Channel	Logic Level Gate

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Bulk	1090	$ 0.28

Description

General part information

FDC6302P Series

These Dual P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load switchimg applications. Since bias resistors are not required this one P-Channel FET can replace several digital transistors with different bias resistors like the IMBxA series.