Specification	CDC906PWR

Differential - Input:Output	Yes/No
Frequency - Max [Max]	167 MHz
Input	LVCMOS, Crystal
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output	LVCMOS
Package / Case	20-TSSOP
Package / Case [x]	0.173 in
Package / Case [y]	4.4 mm
PLL	Yes with Bypass
Ratio - Input:Output [custom]	1:6
Supplier Device Package	20-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

CDC906 Series

167-MHz, LVCMOS, custom-programmed 3-PLL clock synthesizer, multiplier & divider

Part	Frequency - Max [Max]	Differential - Input:Output	Number of Circuits	Package / Case [y]	Package / Case	Package / Case [x]	PLL	Voltage - Supply [Max]	Voltage - Supply [Min]	Output	Mounting Type	Operating Temperature [Max]	Input	Ratio - Input:Output [custom]	Supplier Device Package
Texas Instruments CDC906PWR	167 MHz	Yes/No	1	4.4 mm	20-TSSOP	0.173 in	Yes with Bypass	3.6 V	3 V	LVCMOS	Surface Mount	70 °C	Crystal LVCMOS	1:6	20-TSSOP
Texas Instruments CDC906PWRG4	167 MHz	Yes/No	1	4.4 mm	20-TSSOP	0.173 in	Yes with Bypass	3.6 V	3 V	LVCMOS	Surface Mount	70 °C	Crystal LVCMOS	1:6	20-TSSOP
Texas Instruments CDC906PW	167 MHz	Yes/No	1	4.4 mm	20-TSSOP	0.173 in	Yes with Bypass	3.6 V	3 V	LVCMOS	Surface Mount	70 °C	Crystal LVCMOS	1:6	20-TSSOP
Texas Instruments CDC906PWG4	167 MHz	Yes/No	1	4.4 mm	20-TSSOP	0.173 in	Yes with Bypass	3.6 V	3 V	LVCMOS	Surface Mount	70 °C	Crystal LVCMOS	1:6	20-TSSOP

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	2000	$ 2.99
Texas Instruments	LARGE T&R	1	$ 4.71
		100	$ 3.84
		250	$ 3.02
		1000	$ 2.56

Description

General part information

CDC906 Series

The CDC906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDC906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

Documents

Technical documentation and resources

Programmable 3-PLL Clock Synthesizer / Multiplier / Divider datasheet (Rev. B)

Data sheet