BD3533F-E2
Active3A VARIABLE OUTPUT TERMINATION REGULATOR FOR DDR-SDRAMS
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BD3533F-E2
Active3A VARIABLE OUTPUT TERMINATION REGULATOR FOR DDR-SDRAMS
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Technical Specifications
Parameters and characteristics for this part
| Specification | BD3533F-E2 |
|---|---|
| Applications | DDR Bus Termination Regulator, Converter |
| Mounting Type | Surface Mount |
| Number of Outputs | 1 |
| Operating Temperature [Max] | 100 °C |
| Operating Temperature [Min] | -20 ░C |
| Package / Case | 8-SOIC (0.173", 4.40mm Width) |
| Supplier Device Package | 8-SOP |
| Voltage - Input [Max] | 5.5 V |
| Voltage - Input [Min] | 2.7 V |
| Voltage - Output | Multiple |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 1.37 | |
Description
General part information
BD3533F Series
BD3533F is a termination regulator that complies with JEDEC requirements for DDR-SDRAM. This linear power supply uses a built-in N-channel MOSFET and high-speed OP-AMPS specially designed to provide excellent transient response. It has a sink/source current capability up to 1A and has a power supply bias requirement of 3.3V to 5.0V for driving the N-channel MOSFET. By employing an independent reference voltage input (VDDQ) and a feedback pin (VTTS), this termination regulator provides excellent output voltage accuracy and load regulation as required by JEDEC standards. Additionally, BD3533 has a reference power supply output (VREF) for DDR-SDRAM or for memory controllers. Unlike the VTT output that goes to "Hi-Z" state, the VREF output is kept unchanged when EN input is changed to "Low", making this IC suitable for DDR-SDRAM under "Self Refresh" state.
Documents
Technical documentation and resources