74HC4520PW-Q100J
ActiveDUAL 4-BIT SYNCHRONOUS BINARY COUNTER
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74HC4520PW-Q100J
ActiveDUAL 4-BIT SYNCHRONOUS BINARY COUNTER
Technical Specifications
Parameters and characteristics for this part
| Specification | 74HC4520PW-Q100J |
|---|---|
| Count Rate | 69 MHz |
| Direction | Up |
| Grade | Automotive |
| Logic Type | Binary Counter |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 4 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 16-TSSOP |
| Package / Case [y] | 4.4 mm |
| Package / Case [y] | 0.173 in |
| Qualification | AEC-Q100 |
| Reset | Asynchronous |
| Supplier Device Package | 16-TSSOP |
| Timing | Synchronous |
| Trigger Type | Negative, Positive |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 0.36 | |
| 0 | $ 0.57 | |||
Description
General part information
74HC4520PW-Q100 Series
The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Documents
Technical documentation and resources