The 74HC109; 74HCT109 is a dual positive edge triggered JKflip-flop featuring individual J andKinputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q andQoutputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J andKinputs control the state changes of the flip-flops as described in the mode select function table. The J andKinputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JKdesign allows operation as a D-type flip-flop by connecting the J andKinputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.