
SCAN921821TSM/NOPB
ActiveDUAL 18-BIT SERIALIZER WITH PRE-EMPHASIS, IEEE 1149.1 (JTAG), AND AT-SPEED BIST
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SCAN921821TSM/NOPB
ActiveDUAL 18-BIT SERIALIZER WITH PRE-EMPHASIS, IEEE 1149.1 (JTAG), AND AT-SPEED BIST
Technical Specifications
Parameters and characteristics for this part
| Specification | SCAN921821TSM/NOPB |
|---|---|
| Data Rate | 2.38 Gbps |
| Function | Serializer |
| Input Type | LVTTL, LVCMOS |
| Mounting Type | Surface Mount |
| Number of Inputs | 18 |
| Number of Outputs | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | LVDS |
| Package / Case | 100-LFBGA |
| Supplier Device Package | 100-FBGA (10x10) |
| Voltage - Supply [Max] | 3.45 V |
| Voltage - Supply [Min] | 3.15 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 240 | $ 12.33 | |
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 13.08 | |
| 100 | $ 11.42 | |||
| 250 | $ 8.81 | |||
| 1000 | $ 7.88 | |||
Description
General part information
SCAN921821 Series
The SCAN921821 is a dual channel 18-bit serializer featuring signal conditioning, boundary SCAN, and at-speed BIST. Each serializer block transforms an 18-bit parallel LVCMOS/LVTTL data bus into a single Bus LVDS data stream with embedded clock. This single serial data stream with embedded clock simplifies PCB design and reduces PCB cost by narrowing data paths that in turn reduce PCB size and layers. The single serial data stream also reduces cable size, the number of connectors, and eliminates clock-to-data and data-to-data skew.
Each channel also has an 8-level selectable pre-emphasis feature that significantly extends performance over lossy interconnect. Each channel also has its own powerdown pin that saves power by reducing supply current when the channel is not being used.
The SCAN921821 also incorporates advanced testability features including IEEE 1149.1 and at-speed BIST PRBS pattern generation to facilitate verification of board and link integrity
Documents
Technical documentation and resources