LMK03000CISQ/NOPB
Active1185 TO 1296-MHZ, 800FS RMS JITTER, PRECISION CLOCK CONDITIONER WITH INTEGRATED VCO
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LMK03000CISQ/NOPB
Active1185 TO 1296-MHZ, 800FS RMS JITTER, PRECISION CLOCK CONDITIONER WITH INTEGRATED VCO
Technical Specifications
Parameters and characteristics for this part
| Specification | LMK03000CISQ/NOPB |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Divider/Multiplier | Yes/No |
| Frequency - Max [Max] | 1.296 GHz |
| Input | LVDS, LVCMOS, LVPECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVPECL, LVDS |
| Package / Case | 48-WFQFN Exposed Pad |
| PLL | False |
| Ratio - Input:Output | 1:8 |
| Supplier Device Package | 48-WQFN (7x7) |
| Type | Clock Conditioner |
| Voltage - Supply [Max] | 3.45 V |
| Voltage - Supply [Min] | 3.15 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 22.97 | |
| 10 | $ 18.41 | |||
| 25 | $ 17.27 | |||
| 100 | $ 16.02 | |||
| Digi-Reel® | 1 | $ 22.97 | ||
| 10 | $ 18.41 | |||
| 25 | $ 17.27 | |||
| 100 | $ 16.02 | |||
| Tape & Reel (TR) | 250 | $ 15.42 | ||
| 500 | $ 15.07 | |||
| Texas Instruments | SMALL T&R | 1 | $ 18.23 | |
| 100 | $ 15.92 | |||
| 250 | $ 12.28 | |||
| 1000 | $ 10.98 | |||
Description
General part information
LMK03000 Series
The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.
The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks.
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
Documents
Technical documentation and resources