Integrated Circuits (ICs)

CDCVF2509APWR

Obsolete

Texas Instruments

IC PLL CLOCK DRIVER 24TSSOP

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Integrated Circuits (ICs)

CDCVF2509APWR

Obsolete

Texas Instruments

IC PLL CLOCK DRIVER 24TSSOP

Deep-Dive with AI

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CDCVF2509APWR

Differential - Input:Output	False
Divider/Multiplier	False
Frequency - Max [Max]	175 MHz
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	0 °C
Output	LVTTL
Package / Case	24-TSSOP
Package / Case	0.173 in, 4.4 mm
PLL	Yes with Bypass
Ratio - Input:Output [custom]	10
Ratio - Input:Output [custom]	2
Supplier Device Package	24-TSSOP
Type	PLL Clock Driver
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

CDCVF2509 Series

3.3-V phase-lock loop clock driver with 9 outputs for DRAM applications

Part	Frequency - Max [Max]	Output	PLL	Operating Temperature [Max]	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Package / Case	Type	Number of Circuits	Supplier Device Package
Texas Instruments CDCVF2509PWG4	175 MHz	LVTTL	Yes with Bypass	85 °C	10	2	Surface Mount	3.6 V	3 V	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	1	24-TSSOP
Texas Instruments CDCVF2509PW	175 MHz	LVTTL	Yes with Bypass	85 °C	10	2	Surface Mount	3.6 V	3 V	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	1	24-TSSOP
Texas Instruments CDCVF2509APW	175 MHz	LVTTL	Yes with Bypass	85 °C	10	2	Surface Mount	3.6 V	3 V	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	1	24-TSSOP
Texas Instruments CDCVF2509APWR	175 MHz	LVTTL	Yes with Bypass	85 °C	10	2	Surface Mount	3.6 V	3 V	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	1	24-TSSOP

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

CDCVF2509 Series

The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The device uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The device is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at a 3.3V VCCand provides integrated series-damping resistors designed for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately through the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK. When the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Documents

Technical documentation and resources

No documents available