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20-SOIC
Integrated Circuits (ICs)

CY74FCT377ATSOCTG4

Obsolete
Texas Instruments

IC FF D-TYPE SNGL 8BIT 20SOIC

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20-SOIC
Integrated Circuits (ICs)

CY74FCT377ATSOCTG4

Obsolete
Texas Instruments

IC FF D-TYPE SNGL 8BIT 20SOIC

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCY74FCT377ATSOCTG4
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Current - Quiescent (Iq)200 µA
FunctionStandard
Input Capacitance5 pF
Max Propagation Delay @ V, Max CL7.2 ns
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeNon-Inverted
Package / Case20-SOIC
Package / Case [y]0.295 in
Package / Case [y]7.5 mm
Supplier Device Package20-SOIC
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

CY74FCT377T Series

The \x92FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE\) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop output (O). CE\ must be stable only one setup time prior to the low-to-high clock transition for predictable operation.

These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE\) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop output (O). CE\ must be stable only one setup time prior to the low-to-high clock transition for predictable operation.

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Technical documentation and resources

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