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Technical Specifications
Parameters and characteristics for this part
| Specification | TMS5700432APZQQ1 |
|---|---|
| Connectivity | LINbus, SCI, SPI, CANbus, MibSPI, UART/USART |
| Core Processor | ARM® Cortex®-R4 |
| Core Size [Max] | 32 Bit |
| Core Size [Min] | 16 Bit |
| Data Converters [custom] | 16 |
| Data Converters [custom] | 12 b |
| EEPROM Size | 16 K |
| Grade | Automotive |
| Mounting Type | Surface Mount |
| Number of I/O | 45 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | External |
| Package / Case | 100-LQFP |
| Peripherals | POR, PWM, WDT |
| Program Memory Size | 384 KB |
| Program Memory Type | FLASH |
| Qualification | AEC-Q100 |
| Speed | 80 MHz |
| Supplier Device Package | 100-LQFP (14x14) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.14 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
TMS570LS0714-S Series
The TMS570LS0714 device is part of theHerculesTMS570 series of high-performance automotive-grade ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the development of ISO 26262 and IEC 61508 functional safety applications. Start evaluating today with the HerculesHercules TMS570 LaunchPad Development Kit. The TMS570LS0714 device has on-chip diagnostic features including: dual CPUs in lockstep; CPU and memory Built-In Self-Test (BIST) logic; ECC on both the flash and the SRAM; parity on peripheral memories; and loopback capability on most peripheral I/Os.
The TMS570LS0714 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and has configurations which can run up to 160 MHz providing up to 265 DMIPS. The TMS570 device supports the word invariant big-endian [BE32] format.
The TMS570LS0714 device has 768KB of integrated flash and 128KB of RAM configurations with single-bit error correction and double-bit error detection. The flash memory on this device is nonvolatile, electrically erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as the I/O supply) for all read, program, and erase operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and doubleword modes throughout the supported frequency range.
Documents
Technical documentation and resources
